1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising flip flops (FF) and combination circuits and a test pattern generation method for generating test patterns used for detecting faulty circuits involved in the semiconductor integrated circuit.
2. Description of the Related Art
In general, a semiconductor integrated circuit comprises a plurality of flip flops (FF) and a plurality of combination circuits. Recently, there have been strong demands to provide Large Scale Integration (LSI) circuits operable in a higher frequency in the semiconductor integrated circuit field. In order to achieve this demand, the number of flip flops and the area required for the flip flops in the semiconductor integrated circuit have increased.
FIG. 1 is a block diagram showing a part of a conventional semiconductor integrated circuit. In FIG. 1, the reference character FF designates a flip flop, 11a, 11b, 11c, 11d, and 11e denote stages. Each stage comprises a plurality of the flip flops (FF). The reference characters 2a, 2b, 2c, and 2d indicate combination circuits.
There are conventional test circuit design methods such as a full scan and a partial scan in which flip flops (FF) are replaced with scan flip flop (SFF) in order to detect faulty circuits in a plurality of the flip flops (FF) and the combination circuits, and wiring defects in the semiconductor integrated circuit. The conventional test circuit design methods use an Auto Test Pattern Generation (ATPG) to generate test patterns automatically.
FIG. 2 is an explanation circuit showing a full scan test method. In FIG. 2, the reference characters 12a, 12b, 12c, 12d, and 12e designate stages. The reference number 12 denotes a scan chain through which test patterns are transferred from an external device such as an external tester (not shown) to the scan flip flops (SFF) in each stage. That is, through the scan chain 12, the scan flip flops (SFF) in the stages 12a to 12e are connected in series. Other circuit components shown in FIG. 2 are the same as the circuit components in the semiconductor integrated circuit shown in FIG. 1. Therefore the same reference characters are used for the same components.
Next, a description will be given of the operation of the conventional test pattern generation method.
In the full scan method, the scan chain 12 is formed by connecting the scan flip flops (SFF) in the stage 12a, 12b, 12c, 12d, and 12e in series. During the scan mode, the test pattern is set into the scan flip flops (SFF) through the scan chain 12. During a normal mode after this scan mode, a clock signal is supplied so that the combination circuits 2a, 2b, 2c, and 2d input the test pattern from the scan flip flops (SFF) in each of the stages 12a, 12b, 12c, 12d, and 12e and then output the test patterns. Further, during the scan mode after this normal mode, the scan flip flops (SFF) in each stage input the test pattern from the combination circuits 2a, 2b, 2c, and 2d. After this, the external tester (not shown) monitors the test result obtained by the above test operation to detect the presence or absence of circuit defects or wiring defects in the semiconductor integrated circuit.
FIG. 3 is a flow chart showing the procedure of the full scan method.
First, the combination circuits 2a, 2b, 2c, and 2d in the semiconductor integrated circuit are extracted (Step ST131). Next, the ATPG is executed for the combination circuits 2a, 2b, 2c, and 2d (Step ST132). Since the test pattern generated by the ATPG controls the input to and output from each of the combination circuits 2a, 2b, 2c, and 2d, it cannot be directly used for the test of an actual semiconductor integrated circuit.
Next, the formatting of the test pattern generated by the ATPG is executed in order to use the test pattern for the actual semiconductor integrated circuit (Step ST133). For example, in the formatting of the test pattern used for testing of the combination circuit 2a, the test pattern is set into the scan flip flop (SFF) in the first stage 12a through the scan chain 12. After this, during the normal operation mode, the scan flip flops (SFF) in the stage 12b input the output from the combination circuit 2a during one system clock. Finally, the data stored in the scan flip flops (SFF) in the stage 12b are transferred to the external device such as the external tester (not shown) through the scan chain 12 during the scan operation mode.
In general, the above described operations are repeated required times for the formatting of the test patterns because the ATPG generates many test patterns. In this case, the test patterns may be generated only for small scale combination circuits that are divided by the scan chain 12. Accordingly, the test patterns are relatively generated and it is possible to increase the rate of the detection of faulty circuits by using the small scale test patterns.
However, the circuit area of the semiconductor integrated circuit is increased because all of the flip flops in the semiconductor integrated circuit are replaced with the scan flip flops in the full scan method. The rate of the increasing of the area is proportional to the number of the flip flops.
The difference in area between the flip flop (FF) and the scan flip flop (SFF) will be explained.
FIG. 4 is a block diagram showing a configuration of a flip flop (FF). FIG. 5 is a block diagram showing a configuration of a scan flip flop (SFF). In FIG. 4 and FIG. 5, the reference character D designates a data input line through which a data item is inputted, and SI denotes an input data line through which a scan data item is inputted. The reference character SM in FIG. 5 denotes a control line through which a control signal to set the scan flip flop (SFF) into the scan operation mode is inputted. The reference character T designates an input line through which a scan clock is inputted. This scan clock controls the operation of the scan flip flop (SFF). The reference character Q indicates an output line through which the data is outputted. The reference character QC designates an output line through which an inverted data item that is obtained by inverting the level of the data on the output line Q is outputted.
As clearly shown in FIG. 4 and FIG. 5, the scan flip flop (SFF) shown in FIG. 5 is larger in circuit size than the flip flop (FF) shown in FIG. 4. That is, the scan flip flop (SFF) shown in FIG. 5 has a larger circuit area when compared with the flip flop (FF).
Recently, there have been strong demands to provide a semiconductor integrated circuit operable in a high frequency. In order to achieve this demand, the number of stages made up of combination circuits must be decreased. Each of the combination circuits are placed between stages made up of flip flops (FF). This means an increase in the number of the flip flops (FF). Accordingly, the application of the full scan to a semiconductor integrated circuit introduces a drawback that the overhead of the circuit area in the semiconductor integrated circuit is increased because all of the flip flops (FF) must be replaced with the scan flip flops (SFFs) in the full scan.
FIG. 6 is a diagram explaining a procedure of a partial scan operation. In FIG. 6, the reference characters 16a, 16b, 16c, 16d, and 16e designate stages. The stages other than the stage 16c include both flip flops and scan flip flops. In the configuration shown in FIG. 6, all of the scan flip flop (SFF) are connected to each other through a scan chain 16. Other circuit components shown in FIG. 6 are the same of the circuit components of the semiconductor integrated circuit shown in FIG. 1. Accordingly, the same reference characters are used for the same circuit components.
Next, a description will be given of the operation of the partial scan.
FIG. 7 is a flowchart showing the procedure of the partial scan operation.
When the partial scan is executed for the target semiconductor integrated circuit shown in FIG. 1, at first, the circuit configuration of the semiconductor integrated circuit is analyzed in order to extract test points including flip flops having poor controlling and poor observation (Step ST171). Those test points are arranged in the order of the poor control.
Next, the number of the flip flops that will be replaced with the scan flip flops is determined based on a predetermined scan rate. This scan rate is a rate of the number of the flip flops to be replaced with the scan flip flops to the total number of the flip flops in the target semiconductor integrated circuit. The number of the flip flops to be replaced is obtained by multiplying the total number of the flip flops with the scan rate. Then, the flip flops in the test points are extracted according to the number of the flip flops obtained by the above multiplication. Further, the flip flops extracted are replaced with the scan flip flops (SFF) (Step ST172). Thereby, the circuit including the scan chain 16 shown in FIG. 6 is obtained.
Next, taking into consideration in the control and observation using the scan chain 16, the ATPG is executed for the circuits including the scan flip flops shown in FIG. 6 in order to generate test patterns (Step ST173). However, when compared with the full scan operation, this partial scan operation further requires the generation of other test patterns for sequential circuits such as flip flops based on the timing of a system clock because the target circuits for the ATPG includes sequential circuits such as the flip flops.
Finally, like the full scan operation, the formatting of the test patterns is executed in order to correctly set and observe the data to the parts connected through the scan chain 16 (Step ST174).
Because the partial scan operation does not require replacing all of the flip flops with the scan flip flops, it is possible to decrease the scan rate and to suppress the overhead of the circuit area of the replaced scan flip flop in the target semiconductor integrated circuit when compared with the full scan operation. However, it is difficult in a partial scan to execute the ATPG while taking into consideration of the sequential circuits such as flip flops. Accordingly, when the scan rate is decreased, the detection rate of detecting faulty circuits is also decreased. This greatly increases the number of test patterns in order to increase the detection rate to detect faulty circuits and wiring defects. In addition to this drawback, it is very difficult in function for a current engineering work station (EWS) to execute the partial scan operation for a large scale integration (LSI), because the partial scan requires to generate test patterns while taking into consideration for the sequential circuits such as flip flops.
Since the conventional test methods, the full scan method and the partial scan method, to detect faulty circuits and wiring defects in the semiconductor integrated circuit are executed based on the procedures described above, flip flops (FF) must be replaced with scan flip flops (SFF) in the full scan operation. This increases the circuit area of the semiconductor integrated circuit, namely to increase the overhead of the area of the semiconductor integrated circuit. On the other hand, because some flip flops in the semiconductor integrated circuit are replaced with scan flip flops (SFF) in the partial scan operation, it is possible to suppress the overhead of the area of the semiconductor integrated circuit, but it becomes difficult to execute the ATPG while taking into consideration of the sequential circuits such as the flip flops. For example, the partial scan decreases the rate of the detection of faulty circuits and increases the number of test patterns when the scan rate is decreased. In addition, because the partial scan must generate the test patterns while taking into consideration of the sequential circuits such as flip flops, it is required to generate the test patterns while considering the entire circuit configuration of the semiconductor integrated circuit. It is therefor difficult in function for the current engineering work station (EWS) to execute the partial scan for the large scale integration (LSI).
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a semiconductor integrated circuit and a test pattern generation method therefor, whose configuration and method are capable of suppressing the overhead of the area and detecting faulty circuits and wiring defects with a high detection rate, and introduce easy generation of test patterns. That is to say, the ATPG may be easily executed,
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit comprises a plurality of stages, each stage including a plurality of flip flops, and every nth stages being connected to each other to form a scan chain for a scan test, where n is an integer, a plurality of combination circuits respectively placed among said plurality of stages, a first test path connected between said plurality of stages so as to ensure that a given stage is assigned a plurality of stage labels such that integer subscripts respectively constituting said plurality of stage labels produce the same remainder when divided by the integer n, and a first test circuit placed on said first test path, said first test circuit selectively actuating said first test path in a scan test.
In accordance with another preferred embodiment of the present invention, a test pattern generation method for a semiconductor integrated circuit, comprises the steps of: assigning a plurality of stage labels to each of a plurality of stages constituting the semiconductor integrated circuit, a plurality of flip flops constituting each of said plurality of stages and every nth stages being connected to each other to form a scan chain for a scan test, where n is an integer; inserting a first test path connecting said plurality of stages so as to ensure that a given stage is assigned a plurality of stage labels such that integer subscripts respectively constituting said plurality of stage labels produce the same remainder when divided by the integer n; inserting a first test circuit on the first test path, said first test circuit selectively actuating said first test path in a scan test; replacing said plurality of flip flops in said given stage forming said chain with scan flip flops; and generating test patterns for combination circuits placed between said plurality of stages.